`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:48:57 02/22/2006
// Design Name:   test
// Module Name:   test_test.v
// Project Name:  Memec-test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: test
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_test_v;

   // Inputs
   reg CLK;
   reg [2:1] PUSH;
   reg [3:0] DIP;
   reg [3:0] FIFO_DOUT;
   reg 	     FIFO_FULL;
   reg 	     FIFO_EMPTY;

   // Outputs
   wire [6:0] DISPLAY;
   wire [3:0] LED;
   wire [3:0] FIFO_DIN;
   wire       FIFO_RDCLK;
   wire       FIFO_RDEN;
   wire       FIFO_WRCLK;
   wire       FIFO_WREN;
   wire       FIFO_RESET;

   // Instantiate the Unit Under Test (UUT)
   test uut (
	     .CLK(CLK), 
	     .PUSH(PUSH), 
	     .DIP(DIP), 
	     .DISPLAY(DISPLAY), 
	     .LED(LED), 
	     .FIFO_DIN(FIFO_DIN), 
	     .FIFO_DOUT(FIFO_DOUT), 
	     .FIFO_RDCLK(FIFO_RDCLK), 
	     .FIFO_RDEN(FIFO_RDEN), 
	     .FIFO_WRCLK(FIFO_WRCLK), 
	     .FIFO_WREN(FIFO_WREN), 
	     .FIFO_RESET(FIFO_RESET), 
	     .FIFO_FULL(FIFO_FULL), 
	     .FIFO_EMPTY(FIFO_EMPTY)
	     );

   initial begin
      // Initialize Inputs
      CLK = 0;
      PUSH = 0;
      DIP = 0;
      FIFO_DOUT = 0;
      FIFO_FULL = 0;
      FIFO_EMPTY = 0;

      // Wait 100 ns for global reset to finish
      #100;
   end

   always begin
      #5 CLK = ~CLK; // Toggle clock every 5 ticks
   end
   
endmodule