view fifo.asy @ 3:65ee845bf08c default tip

Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
parents f88da01700da
children
line wrap: on
line source

Version 4
SymbolType BLOCK
RECTANGLE Normal 32 0 352 448
PIN 192 480  BOTTOM 36
PINATTR PinName ainit
PINATTR Polarity IN
LINE Normal 192 448 192 480
PIN 0 48  LEFT 36
PINATTR PinName din[3:0]
PINATTR Polarity IN
LINE Wide 0 48 32 48
PIN 0 144  LEFT 36
PINATTR PinName wr_en
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 176  LEFT 36
PINATTR PinName wr_clk
PINATTR Polarity IN
LINE Normal 0 176 32 176
PIN 0 368  LEFT 36
PINATTR PinName rd_en
PINATTR Polarity IN
LINE Normal 0 368 32 368
PIN 0 400  LEFT 36
PINATTR PinName rd_clk
PINATTR Polarity IN
LINE Normal 0 400 32 400
PIN 384 48  RIGHT 36
PINATTR PinName full
PINATTR Polarity OUT
LINE Normal 352 48 384 48
PIN 384 240  RIGHT 36
PINATTR PinName dout[3:0]
PINATTR Polarity OUT
LINE Wide 352 240 384 240
PIN 384 272  RIGHT 36
PINATTR PinName empty
PINATTR Polarity OUT
LINE Normal 352 272 384 272