# HG changeset patch
# User Daniel O'Connor <darius@dons.net.au>
# Date 1740464612 -37800
# Node ID 6070d2e66b4cf6b7f4d0feeec0d3b1aae11a184c
# Parent  c7845db23ab20f8dacd81f12bee21d9d34b146eb
Cascade IRQs from DAC to control so manual & external trigger are the same.

diff -r c7845db23ab2 -r 6070d2e66b4c ctrl.pio
--- a/ctrl.pio	Tue Feb 25 16:47:00 2025 +1030
+++ b/ctrl.pio	Tue Feb 25 16:53:32 2025 +1030
@@ -3,11 +3,13 @@
 ;
 
 .program ctrl
-.define TRIGGER_IRQ 1
+.define DAC_TRIGGER_IRQ 0
+.define CTRL_TRIGGER_IRQ 1
+
 ; Assert all 0s
     mov pins, null
 ; Wait for start trigger and clear IRQ
-    wait 1 irq TRIGGER_IRQ
+    wait 1 irq CTRL_TRIGGER_IRQ
 .wrap_target
     out pins 8
     nop
diff -r c7845db23ab2 -r 6070d2e66b4c dac.pio
--- a/dac.pio	Tue Feb 25 16:47:00 2025 +1030
+++ b/dac.pio	Tue Feb 25 16:53:32 2025 +1030
@@ -3,7 +3,9 @@
 ;
 
 .program dac
-.define TRIGGER_IRQ 0
+.define DAC_IRQ 0
+.define DAC_TRIGGER_IRQ 0
+.define CTRL_TRIGGER_IRQ 1
 ; Need 1 side set pin, the clock
 .side_set 1
 
@@ -11,7 +13,9 @@
     mov pins, null side 0
     nop side 1
 ; Wait for start trigger and clear IRQ
-    wait 1 irq TRIGGER_IRQ side 0
+    wait 1 irq DAC_TRIGGER_IRQ side 0
+; Trigger the control SM
+    irq nowait CTRL_TRIGGER_IRQ side 0
 ; Clock DAC and write data from the FIFO
 ; DAC clocks data in on the rising clock edge
 .wrap_target
diff -r c7845db23ab2 -r 6070d2e66b4c modulator.c
--- a/modulator.c	Tue Feb 25 16:47:00 2025 +1030
+++ b/modulator.c	Tue Feb 25 16:53:32 2025 +1030
@@ -16,7 +16,7 @@
 ** Create modulation shape
 **
 */
-#define WITH_TRIGGER
+//#define WITH_TRIGGER
 
 #include <stdio.h>
 #include <string.h>
@@ -125,8 +125,8 @@
   pwm_clear_irq(slice_num);
 
 #ifndef WITH_TRIGGER
-  // Manually trigger DAQ SM (cleared by SM)
-  pulse_pio->irq_force = 3;
+  // Manually trigger DAC SM (cleared by SM)
+  pulse_pio->irq_force = 1;
 
   // 'scope trigger
   gpio_put(2, 1);
diff -r c7845db23ab2 -r 6070d2e66b4c trigger.pio
--- a/trigger.pio	Tue Feb 25 16:47:00 2025 +1030
+++ b/trigger.pio	Tue Feb 25 16:53:32 2025 +1030
@@ -13,9 +13,8 @@
     wait 0 pin 0 side 0
 ; Wait for rising edge
     wait 1 pin 0 side 0
-; Signal other state machines
+; Signal DAC SM (which will trigger the control one)
     irq nowait DAC_TRIGGER_IRQ side 1
-    irq nowait CTRL_TRIGGER_IRQ side 1
 .wrap
 
 % c-sdk {