# HG changeset patch
# User darius
# Date 1140789685 0
# Node ID f88da01700da752b1b1069c3abbd0f5f18a621b5
# Parent  7390b436dd2055cd00a8e5702759c74aa7637c87
Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.

Uses a FIFO and flashes some LEDs.

diff -r 7390b436dd20 -r f88da01700da fifo.asy
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.asy	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,39 @@
+Version 4
+SymbolType BLOCK
+RECTANGLE Normal 32 0 352 448
+PIN 192 480  BOTTOM 36
+PINATTR PinName ainit
+PINATTR Polarity IN
+LINE Normal 192 448 192 480
+PIN 0 48  LEFT 36
+PINATTR PinName din[3:0]
+PINATTR Polarity IN
+LINE Wide 0 48 32 48
+PIN 0 144  LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 176  LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 368  LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 368 32 368
+PIN 0 400  LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 0 400 32 400
+PIN 384 48  RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 352 48 384 48
+PIN 384 240  RIGHT 36
+PINATTR PinName dout[3:0]
+PINATTR Polarity OUT
+LINE Wide 352 240 384 240
+PIN 384 272  RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Normal 352 272 384 272
diff -r 7390b436dd20 -r f88da01700da fifo.edn
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.edn	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,1691 @@
+(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
+(status (written (timeStamp 2006 2 21 15 55 25)
+   (author "Xilinx, Inc.")
+   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.1.02i; Cores Update # 1"))))
+   (comment "                                                                                
+      This file is owned and controlled by Xilinx and must be used              
+      solely for design, simulation, implementation and creation of             
+      design files limited to Xilinx devices or technologies. Use               
+      with non-Xilinx devices or technologies is expressly prohibited           
+      and immediately terminates your license.                                  
+                                                                                
+      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
+      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
+      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
+      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
+      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
+      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
+      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
+      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
+      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
+      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
+      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
+      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
+      FOR A PARTICULAR PURPOSE.                                                 
+                                                                                
+      Xilinx products are not intended for use in life support                  
+      appliances, devices, or systems. Use in such applications are             
+      expressly prohibited.                                                     
+                                                                                
+      (c) Copyright 1995-2006 Xilinx, Inc.                                      
+      All rights reserved.                                                      
+                                                                                
+   ")
+   (comment "Core parameters: ")
+       (comment "c_use_blockmem = 1 ")
+       (comment "c_rd_count_width = 2 ")
+       (comment "c_has_wr_ack = 0 ")
+       (comment "c_has_almost_full = 0 ")
+       (comment "c_has_wr_err = 0 ")
+       (comment "c_wr_err_low = 0 ")
+       (comment "c_wr_ack_low = 0 ")
+       (comment "c_data_width = 4 ")
+       (comment "c_enable_rlocs = 0 ")
+       (comment "c_rd_err_low = 0 ")
+       (comment "c_rd_ack_low = 0 ")
+       (comment "c_wr_count_width = 2 ")
+       (comment "InstanceName = fifo ")
+       (comment "c_has_rd_count = 0 ")
+       (comment "c_has_almost_empty = 0 ")
+       (comment "c_has_rd_ack = 0 ")
+       (comment "c_has_wr_count = 0 ")
+       (comment "c_fifo_depth = 15 ")
+       (comment "c_has_rd_err = 0 ")
+   (external xilinxun (edifLevel 0)
+      (technology (numberDefinition))
+       (cell VCC (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port P (direction OUTPUT))
+               )
+           )
+       )
+       (cell GND (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port G (direction OUTPUT))
+               )
+           )
+       )
+       (cell FDC (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port D (direction INPUT))
+                   (port C (direction INPUT))
+                   (port CLR (direction INPUT))
+                   (port Q (direction OUTPUT))
+               )
+           )
+       )
+       (cell FDCE (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port D (direction INPUT))
+                   (port C (direction INPUT))
+                   (port CE (direction INPUT))
+                   (port CLR (direction INPUT))
+                   (port Q (direction OUTPUT))
+               )
+           )
+       )
+       (cell FDP (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port D (direction INPUT))
+                   (port C (direction INPUT))
+                   (port PRE (direction INPUT))
+                   (port Q (direction OUTPUT))
+               )
+           )
+       )
+       (cell FDPE (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port D (direction INPUT))
+                   (port C (direction INPUT))
+                   (port CE (direction INPUT))
+                   (port PRE (direction INPUT))
+                   (port Q (direction OUTPUT))
+               )
+           )
+       )
+       (cell LUT4 (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port I0 (direction INPUT))
+                   (port I1 (direction INPUT))
+                   (port I2 (direction INPUT))
+                   (port I3 (direction INPUT))
+                   (port O (direction OUTPUT))
+               )
+           )
+       )
+       (cell MUXCY (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port DI (direction INPUT))
+                   (port CI (direction INPUT))
+                   (port S (direction INPUT))
+                   (port O (direction OUTPUT))
+               )
+           )
+       )
+       (cell MUXCY_D (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port DI (direction INPUT))
+                   (port CI (direction INPUT))
+                   (port S (direction INPUT))
+                   (port O (direction OUTPUT))
+                   (port LO (direction OUTPUT))
+               )
+           )
+       )
+       (cell MUXCY_L (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port DI (direction INPUT))
+                   (port CI (direction INPUT))
+                   (port S (direction INPUT))
+                   (port LO (direction OUTPUT))
+               )
+           )
+       )
+       (cell RAMB16_S4_S4 (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port WEA (direction INPUT))
+                   (port ENA (direction INPUT))
+                   (port SSRA (direction INPUT))
+                   (port CLKA (direction INPUT))
+                   (port (rename DIA_0_ "DIA<0>") (direction INPUT))
+                   (port (rename DIA_1_ "DIA<1>") (direction INPUT))
+                   (port (rename DIA_2_ "DIA<2>") (direction INPUT))
+                   (port (rename DIA_3_ "DIA<3>") (direction INPUT))
+                   (port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
+                   (port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
+                   (port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
+                   (port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
+                   (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
+                   (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
+                   (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
+                   (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
+                   (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
+                   (port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
+                   (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
+                   (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
+                   (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
+                   (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
+                   (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
+                   (port (rename ADDRA_11_ "ADDRA<11>") (direction INPUT))
+                   (port WEB (direction INPUT))
+                   (port ENB (direction INPUT))
+                   (port SSRB (direction INPUT))
+                   (port CLKB (direction INPUT))
+                   (port (rename DIB_0_ "DIB<0>") (direction INPUT))
+                   (port (rename DIB_1_ "DIB<1>") (direction INPUT))
+                   (port (rename DIB_2_ "DIB<2>") (direction INPUT))
+                   (port (rename DIB_3_ "DIB<3>") (direction INPUT))
+                   (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
+                   (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
+                   (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
+                   (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
+                   (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
+                   (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
+                   (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
+                   (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
+                   (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
+                   (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
+                   (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
+                   (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
+                   (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
+                   (port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT))
+                   (port (rename ADDRB_10_ "ADDRB<10>") (direction INPUT))
+                   (port (rename ADDRB_11_ "ADDRB<11>") (direction INPUT))
+               )
+           )
+       )
+       (cell XORCY (cellType GENERIC)
+           (view view_1 (viewType NETLIST)
+               (interface
+                   (port LI (direction INPUT))
+                   (port CI (direction INPUT))
+                   (port O (direction OUTPUT))
+               )
+           )
+       )
+   )
+(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
+(cell fifo
+ (cellType GENERIC) (view view_1 (viewType NETLIST)
+  (interface
+   (port ( array ( rename din "din<3:0>") 4 ) (direction INPUT))
+   (port ( rename wr_en "wr_en") (direction INPUT))
+   (port ( rename wr_clk "wr_clk") (direction INPUT))
+   (port ( rename rd_en "rd_en") (direction INPUT))
+   (port ( rename rd_clk "rd_clk") (direction INPUT))
+   (port ( rename ainit "ainit") (direction INPUT))
+   (port ( array ( rename dout "dout<3:0>") 4 ) (direction OUTPUT))
+   (port ( rename full "full") (direction OUTPUT))
+   (port ( rename empty "empty") (direction OUTPUT))
+   )
+  (contents
+   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
+   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
+   (instance B8
+      (viewRef view_1 (cellRef RAMB16_S4_S4 (libraryRef xilinxun)))
+      (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_24 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_25 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_26 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_27 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_28 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_29 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_2A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_2B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_2C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_2D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_2E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000"))
+      (property WRITE_MODE_A (string "NO_CHANGE"))
+      (property INIT_A (string "0"))
+      (property SRVAL_A (string "0"))
+      (property WRITE_MODE_B (string "NO_CHANGE"))
+      (property INIT_B (string "0"))
+      (property SRVAL_B (string "0"))
+   )
+   (instance BU17
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "2222"))
+   )
+   (instance BU23
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "2222"))
+   )
+   (instance BU30
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "5555"))
+   )
+   (instance BU31
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU32
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU34
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU36
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "aaaa"))
+   )
+   (instance BU37
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU38
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU40
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU42
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "aaaa"))
+   )
+   (instance BU43
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU44
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU46
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU48
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "aaaa"))
+   )
+   (instance BU49
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU51
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU59
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU60
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU66
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU67
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU73
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU74
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU80
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU81
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU85
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "fffe"))
+   )
+   (instance BU86
+      (viewRef view_1 (cellRef MUXCY_L (libraryRef xilinxun)))
+   )
+   (instance BU87
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU88
+      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
+   )
+   (instance BU89
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU90
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "ffff"))
+   )
+   (instance BU91
+      (viewRef view_1 (cellRef MUXCY_L (libraryRef xilinxun)))
+   )
+   (instance BU92
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU93
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU94
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU95
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU96
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU97
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU98
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU99
+      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
+   )
+   (instance BU100
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU101
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU102
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU103
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU104
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU105
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU106
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU107
+      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
+   )
+   (instance BU108
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU109
+      (viewRef view_1 (cellRef MUXCY_D (libraryRef xilinxun)))
+   )
+   (instance BU111
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "ffff"))
+   )
+   (instance BU112
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU113
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU122
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "2222"))
+   )
+   (instance BU128
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "2222"))
+   )
+   (instance BU135
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "5555"))
+   )
+   (instance BU136
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU137
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU139
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU141
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "aaaa"))
+   )
+   (instance BU142
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU143
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU145
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU147
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "aaaa"))
+   )
+   (instance BU148
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU149
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU151
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU153
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "aaaa"))
+   )
+   (instance BU154
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU156
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU164
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU165
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU171
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU172
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU178
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU179
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU185
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "6666"))
+   )
+   (instance BU186
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU191
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU193
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU195
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU197
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU200
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "fffe"))
+   )
+   (instance BU201
+      (viewRef view_1 (cellRef MUXCY_L (libraryRef xilinxun)))
+   )
+   (instance BU202
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU203
+      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
+   )
+   (instance BU204
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU205
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "ffff"))
+   )
+   (instance BU206
+      (viewRef view_1 (cellRef MUXCY_L (libraryRef xilinxun)))
+   )
+   (instance BU207
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU208
+      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
+   )
+   (instance BU209
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU210
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU211
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU212
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU213
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU214
+      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
+   )
+   (instance BU215
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU216
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU217
+      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
+   )
+   (instance BU218
+      (viewRef view_1 (cellRef FDC (libraryRef xilinxun)))
+   )
+   (instance BU219
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU220
+      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
+   )
+   (instance BU221
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (instance BU222
+      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
+   )
+   (instance BU223
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "99a5"))
+   )
+   (instance BU224
+      (viewRef view_1 (cellRef MUXCY_D (libraryRef xilinxun)))
+   )
+   (instance BU226
+      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
+      (property INIT (string "ffff"))
+   )
+   (instance BU227
+      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
+   )
+   (instance BU228
+      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
+   )
+   (net N0
+    (joined
+      (portRef G (instanceRef GND))
+      (portRef CI (instanceRef BU31))
+      (portRef CI (instanceRef BU32))
+      (portRef CI (instanceRef BU136))
+      (portRef CI (instanceRef BU137))
+      (portRef SSRA (instanceRef B8))
+      (portRef WEB (instanceRef B8))
+      (portRef SSRB (instanceRef B8))
+      (portRef ADDRA_4_ (instanceRef B8))
+      (portRef ADDRA_5_ (instanceRef B8))
+      (portRef ADDRA_6_ (instanceRef B8))
+      (portRef ADDRA_7_ (instanceRef B8))
+      (portRef ADDRA_8_ (instanceRef B8))
+      (portRef ADDRA_9_ (instanceRef B8))
+      (portRef ADDRA_10_ (instanceRef B8))
+      (portRef ADDRA_11_ (instanceRef B8))
+      (portRef ADDRB_4_ (instanceRef B8))
+      (portRef ADDRB_5_ (instanceRef B8))
+      (portRef ADDRB_6_ (instanceRef B8))
+      (portRef ADDRB_7_ (instanceRef B8))
+      (portRef ADDRB_8_ (instanceRef B8))
+      (portRef ADDRB_9_ (instanceRef B8))
+      (portRef ADDRB_10_ (instanceRef B8))
+      (portRef ADDRB_11_ (instanceRef B8))
+      (portRef DIB_0_ (instanceRef B8))
+      (portRef DIB_1_ (instanceRef B8))
+      (portRef DIB_2_ (instanceRef B8))
+      (portRef DIB_3_ (instanceRef B8))
+      (portRef I2 (instanceRef BU17))
+      (portRef I3 (instanceRef BU17))
+      (portRef I2 (instanceRef BU23))
+      (portRef I3 (instanceRef BU23))
+      (portRef I1 (instanceRef BU30))
+      (portRef I2 (instanceRef BU30))
+      (portRef I3 (instanceRef BU30))
+      (portRef I1 (instanceRef BU36))
+      (portRef I2 (instanceRef BU36))
+      (portRef I3 (instanceRef BU36))
+      (portRef I1 (instanceRef BU42))
+      (portRef I2 (instanceRef BU42))
+      (portRef I3 (instanceRef BU42))
+      (portRef I1 (instanceRef BU48))
+      (portRef I2 (instanceRef BU48))
+      (portRef I3 (instanceRef BU48))
+      (portRef I2 (instanceRef BU59))
+      (portRef I3 (instanceRef BU59))
+      (portRef I2 (instanceRef BU66))
+      (portRef I3 (instanceRef BU66))
+      (portRef I2 (instanceRef BU73))
+      (portRef I3 (instanceRef BU73))
+      (portRef I1 (instanceRef BU80))
+      (portRef I2 (instanceRef BU80))
+      (portRef I3 (instanceRef BU80))
+      (portRef I2 (instanceRef BU85))
+      (portRef I3 (instanceRef BU85))
+      (portRef DI (instanceRef BU86))
+      (portRef I0 (instanceRef BU90))
+      (portRef I1 (instanceRef BU90))
+      (portRef I2 (instanceRef BU90))
+      (portRef I3 (instanceRef BU90))
+      (portRef DI (instanceRef BU91))
+      (portRef DI (instanceRef BU97))
+      (portRef D (instanceRef BU98))
+      (portRef C (instanceRef BU98))
+      (portRef CE (instanceRef BU98))
+      (portRef CLR (instanceRef BU98))
+      (portRef DI (instanceRef BU101))
+      (portRef DI (instanceRef BU105))
+      (portRef DI (instanceRef BU109))
+      (portRef I0 (instanceRef BU111))
+      (portRef I1 (instanceRef BU111))
+      (portRef I2 (instanceRef BU111))
+      (portRef I3 (instanceRef BU111))
+      (portRef LI (instanceRef BU112))
+      (portRef I2 (instanceRef BU122))
+      (portRef I3 (instanceRef BU122))
+      (portRef I2 (instanceRef BU128))
+      (portRef I3 (instanceRef BU128))
+      (portRef I1 (instanceRef BU135))
+      (portRef I2 (instanceRef BU135))
+      (portRef I3 (instanceRef BU135))
+      (portRef I1 (instanceRef BU141))
+      (portRef I2 (instanceRef BU141))
+      (portRef I3 (instanceRef BU141))
+      (portRef I1 (instanceRef BU147))
+      (portRef I2 (instanceRef BU147))
+      (portRef I3 (instanceRef BU147))
+      (portRef I1 (instanceRef BU153))
+      (portRef I2 (instanceRef BU153))
+      (portRef I3 (instanceRef BU153))
+      (portRef I2 (instanceRef BU164))
+      (portRef I3 (instanceRef BU164))
+      (portRef I2 (instanceRef BU171))
+      (portRef I3 (instanceRef BU171))
+      (portRef I2 (instanceRef BU178))
+      (portRef I3 (instanceRef BU178))
+      (portRef I1 (instanceRef BU185))
+      (portRef I2 (instanceRef BU185))
+      (portRef I3 (instanceRef BU185))
+      (portRef I2 (instanceRef BU200))
+      (portRef I3 (instanceRef BU200))
+      (portRef DI (instanceRef BU201))
+      (portRef I0 (instanceRef BU205))
+      (portRef I1 (instanceRef BU205))
+      (portRef I2 (instanceRef BU205))
+      (portRef I3 (instanceRef BU205))
+      (portRef DI (instanceRef BU206))
+      (portRef DI (instanceRef BU212))
+      (portRef D (instanceRef BU213))
+      (portRef C (instanceRef BU213))
+      (portRef CE (instanceRef BU213))
+      (portRef CLR (instanceRef BU213))
+      (portRef DI (instanceRef BU216))
+      (portRef DI (instanceRef BU220))
+      (portRef DI (instanceRef BU224))
+      (portRef I0 (instanceRef BU226))
+      (portRef I1 (instanceRef BU226))
+      (portRef I2 (instanceRef BU226))
+      (portRef I3 (instanceRef BU226))
+      (portRef LI (instanceRef BU227))
+    )
+   )
+   (net N1
+    (joined
+      (portRef P (instanceRef VCC))
+      (portRef ENA (instanceRef B8))
+      (portRef CI (instanceRef BU86))
+      (portRef CI (instanceRef BU91))
+      (portRef CI (instanceRef BU97))
+      (portRef CI (instanceRef BU201))
+      (portRef CI (instanceRef BU206))
+      (portRef CI (instanceRef BU212))
+    )
+   )
+   (net N2
+    (joined
+      (portRef ADDRA_3_ (instanceRef B8))
+      (portRef I0 (instanceRef BU153))
+      (portRef Q (instanceRef BU156))
+      (portRef I1 (instanceRef BU178))
+      (portRef I0 (instanceRef BU185))
+    )
+   )
+   (net N3
+    (joined
+      (portRef ADDRA_2_ (instanceRef B8))
+      (portRef DI (instanceRef BU148))
+      (portRef I0 (instanceRef BU147))
+      (portRef Q (instanceRef BU151))
+      (portRef I1 (instanceRef BU171))
+      (portRef I0 (instanceRef BU178))
+    )
+   )
+   (net N4
+    (joined
+      (portRef ADDRA_1_ (instanceRef B8))
+      (portRef DI (instanceRef BU142))
+      (portRef I0 (instanceRef BU141))
+      (portRef Q (instanceRef BU145))
+      (portRef I1 (instanceRef BU164))
+      (portRef I0 (instanceRef BU171))
+    )
+   )
+   (net N5
+    (joined
+      (portRef ADDRA_0_ (instanceRef B8))
+      (portRef DI (instanceRef BU136))
+      (portRef I0 (instanceRef BU135))
+      (portRef Q (instanceRef BU139))
+      (portRef I0 (instanceRef BU164))
+    )
+   )
+   (net N6
+    (joined
+      (portRef ADDRB_3_ (instanceRef B8))
+      (portRef I0 (instanceRef BU48))
+      (portRef Q (instanceRef BU51))
+      (portRef I1 (instanceRef BU73))
+      (portRef I0 (instanceRef BU80))
+    )
+   )
+   (net N7
+    (joined
+      (portRef ADDRB_2_ (instanceRef B8))
+      (portRef DI (instanceRef BU43))
+      (portRef I0 (instanceRef BU42))
+      (portRef Q (instanceRef BU46))
+      (portRef I1 (instanceRef BU66))
+      (portRef I0 (instanceRef BU73))
+    )
+   )
+   (net N8
+    (joined
+      (portRef ADDRB_1_ (instanceRef B8))
+      (portRef DI (instanceRef BU37))
+      (portRef I0 (instanceRef BU36))
+      (portRef Q (instanceRef BU40))
+      (portRef I1 (instanceRef BU59))
+      (portRef I0 (instanceRef BU66))
+    )
+   )
+   (net N9
+    (joined
+      (portRef ADDRB_0_ (instanceRef B8))
+      (portRef DI (instanceRef BU31))
+      (portRef I0 (instanceRef BU30))
+      (portRef Q (instanceRef BU34))
+      (portRef I0 (instanceRef BU59))
+    )
+   )
+   (net N10
+    (joined
+      (portRef ENB (instanceRef B8))
+      (portRef O (instanceRef BU23))
+    )
+   )
+   (net N11
+    (joined
+      (portRef WEA (instanceRef B8))
+      (portRef O (instanceRef BU128))
+    )
+   )
+   (net (rename N22 "din<3>")
+    (joined
+      (portRef (member din 0))
+      (portRef DIA_3_ (instanceRef B8))
+    )
+   )
+   (net (rename N23 "din<2>")
+    (joined
+      (portRef (member din 1))
+      (portRef DIA_2_ (instanceRef B8))
+    )
+   )
+   (net (rename N24 "din<1>")
+    (joined
+      (portRef (member din 2))
+      (portRef DIA_1_ (instanceRef B8))
+    )
+   )
+   (net (rename N25 "din<0>")
+    (joined
+      (portRef (member din 3))
+      (portRef DIA_0_ (instanceRef B8))
+    )
+   )
+   (net (rename N26 "wr_en")
+    (joined
+      (portRef wr_en)
+      (portRef I0 (instanceRef BU122))
+      (portRef I0 (instanceRef BU128))
+      (portRef I0 (instanceRef BU200))
+    )
+   )
+   (net (rename N27 "wr_clk")
+    (joined
+      (portRef wr_clk)
+      (portRef CLKA (instanceRef B8))
+      (portRef C (instanceRef BU87))
+      (portRef C (instanceRef BU92))
+      (portRef C (instanceRef BU102))
+      (portRef C (instanceRef BU106))
+      (portRef C (instanceRef BU139))
+      (portRef C (instanceRef BU145))
+      (portRef C (instanceRef BU151))
+      (portRef C (instanceRef BU156))
+      (portRef C (instanceRef BU165))
+      (portRef C (instanceRef BU172))
+      (portRef C (instanceRef BU179))
+      (portRef C (instanceRef BU186))
+      (portRef C (instanceRef BU203))
+      (portRef C (instanceRef BU204))
+      (portRef C (instanceRef BU208))
+      (portRef C (instanceRef BU209))
+      (portRef C (instanceRef BU210))
+      (portRef C (instanceRef BU214))
+      (portRef C (instanceRef BU218))
+      (portRef C (instanceRef BU222))
+      (portRef C (instanceRef BU228))
+    )
+   )
+   (net (rename N28 "rd_en")
+    (joined
+      (portRef rd_en)
+      (portRef I0 (instanceRef BU17))
+      (portRef I0 (instanceRef BU23))
+      (portRef I0 (instanceRef BU85))
+    )
+   )
+   (net (rename N29 "rd_clk")
+    (joined
+      (portRef rd_clk)
+      (portRef CLKB (instanceRef B8))
+      (portRef C (instanceRef BU34))
+      (portRef C (instanceRef BU40))
+      (portRef C (instanceRef BU46))
+      (portRef C (instanceRef BU51))
+      (portRef C (instanceRef BU60))
+      (portRef C (instanceRef BU67))
+      (portRef C (instanceRef BU74))
+      (portRef C (instanceRef BU81))
+      (portRef C (instanceRef BU88))
+      (portRef C (instanceRef BU89))
+      (portRef C (instanceRef BU93))
+      (portRef C (instanceRef BU94))
+      (portRef C (instanceRef BU95))
+      (portRef C (instanceRef BU99))
+      (portRef C (instanceRef BU103))
+      (portRef C (instanceRef BU107))
+      (portRef C (instanceRef BU113))
+      (portRef C (instanceRef BU191))
+      (portRef C (instanceRef BU193))
+      (portRef C (instanceRef BU195))
+      (portRef C (instanceRef BU197))
+      (portRef C (instanceRef BU202))
+      (portRef C (instanceRef BU207))
+      (portRef C (instanceRef BU217))
+      (portRef C (instanceRef BU221))
+    )
+   )
+   (net (rename N30 "ainit")
+    (joined
+      (portRef ainit)
+      (portRef CLR (instanceRef BU34))
+      (portRef CLR (instanceRef BU40))
+      (portRef CLR (instanceRef BU46))
+      (portRef CLR (instanceRef BU51))
+      (portRef CLR (instanceRef BU60))
+      (portRef CLR (instanceRef BU67))
+      (portRef CLR (instanceRef BU74))
+      (portRef PRE (instanceRef BU81))
+      (portRef PRE (instanceRef BU87))
+      (portRef PRE (instanceRef BU88))
+      (portRef CLR (instanceRef BU89))
+      (portRef CLR (instanceRef BU92))
+      (portRef CLR (instanceRef BU93))
+      (portRef CLR (instanceRef BU94))
+      (portRef CLR (instanceRef BU95))
+      (portRef PRE (instanceRef BU99))
+      (portRef CLR (instanceRef BU102))
+      (portRef CLR (instanceRef BU103))
+      (portRef PRE (instanceRef BU106))
+      (portRef PRE (instanceRef BU107))
+      (portRef PRE (instanceRef BU113))
+      (portRef CLR (instanceRef BU139))
+      (portRef CLR (instanceRef BU145))
+      (portRef CLR (instanceRef BU151))
+      (portRef CLR (instanceRef BU156))
+      (portRef CLR (instanceRef BU165))
+      (portRef CLR (instanceRef BU172))
+      (portRef CLR (instanceRef BU179))
+      (portRef PRE (instanceRef BU186))
+      (portRef PRE (instanceRef BU191))
+      (portRef CLR (instanceRef BU193))
+      (portRef CLR (instanceRef BU195))
+      (portRef PRE (instanceRef BU197))
+      (portRef PRE (instanceRef BU202))
+      (portRef PRE (instanceRef BU203))
+      (portRef CLR (instanceRef BU204))
+      (portRef PRE (instanceRef BU207))
+      (portRef PRE (instanceRef BU208))
+      (portRef CLR (instanceRef BU209))
+      (portRef CLR (instanceRef BU210))
+      (portRef PRE (instanceRef BU214))
+      (portRef CLR (instanceRef BU217))
+      (portRef CLR (instanceRef BU218))
+      (portRef PRE (instanceRef BU221))
+      (portRef PRE (instanceRef BU222))
+      (portRef PRE (instanceRef BU228))
+    )
+   )
+   (net (rename N31 "dout<3>")
+    (joined
+      (portRef (member dout 0))
+      (portRef DOB_3_ (instanceRef B8))
+    )
+   )
+   (net (rename N32 "dout<2>")
+    (joined
+      (portRef (member dout 1))
+      (portRef DOB_2_ (instanceRef B8))
+    )
+   )
+   (net (rename N33 "dout<1>")
+    (joined
+      (portRef (member dout 2))
+      (portRef DOB_1_ (instanceRef B8))
+    )
+   )
+   (net (rename N34 "dout<0>")
+    (joined
+      (portRef (member dout 3))
+      (portRef DOB_0_ (instanceRef B8))
+    )
+   )
+   (net (rename N35 "full")
+    (joined
+      (portRef full)
+      (portRef I1 (instanceRef BU122))
+      (portRef I1 (instanceRef BU128))
+      (portRef I1 (instanceRef BU200))
+      (portRef I3 (instanceRef BU211))
+      (portRef I3 (instanceRef BU215))
+      (portRef I3 (instanceRef BU219))
+      (portRef I3 (instanceRef BU223))
+      (portRef Q (instanceRef BU228))
+    )
+   )
+   (net (rename N36 "empty")
+    (joined
+      (portRef empty)
+      (portRef I1 (instanceRef BU17))
+      (portRef I1 (instanceRef BU23))
+      (portRef I1 (instanceRef BU85))
+      (portRef I3 (instanceRef BU96))
+      (portRef I3 (instanceRef BU100))
+      (portRef I3 (instanceRef BU104))
+      (portRef I3 (instanceRef BU108))
+      (portRef Q (instanceRef BU113))
+    )
+   )
+   (net N905
+    (joined
+      (portRef O (instanceRef BU17))
+      (portRef CE (instanceRef BU34))
+      (portRef CE (instanceRef BU40))
+      (portRef CE (instanceRef BU46))
+      (portRef CE (instanceRef BU51))
+      (portRef CE (instanceRef BU60))
+      (portRef CE (instanceRef BU67))
+      (portRef CE (instanceRef BU74))
+      (portRef CE (instanceRef BU81))
+      (portRef CE (instanceRef BU191))
+      (portRef CE (instanceRef BU193))
+      (portRef CE (instanceRef BU195))
+      (portRef CE (instanceRef BU197))
+      (portRef CE (instanceRef BU202))
+      (portRef CE (instanceRef BU207))
+      (portRef CE (instanceRef BU217))
+      (portRef CE (instanceRef BU221))
+    )
+   )
+   (net N907
+    (joined
+      (portRef CE (instanceRef BU87))
+      (portRef CE (instanceRef BU92))
+      (portRef CE (instanceRef BU102))
+      (portRef CE (instanceRef BU106))
+      (portRef O (instanceRef BU122))
+      (portRef CE (instanceRef BU139))
+      (portRef CE (instanceRef BU145))
+      (portRef CE (instanceRef BU151))
+      (portRef CE (instanceRef BU156))
+      (portRef CE (instanceRef BU165))
+      (portRef CE (instanceRef BU172))
+      (portRef CE (instanceRef BU179))
+      (portRef CE (instanceRef BU186))
+    )
+   )
+   (net N928
+    (joined
+      (portRef Q (instanceRef BU81))
+      (portRef I0 (instanceRef BU108))
+      (portRef D (instanceRef BU197))
+    )
+   )
+   (net N929
+    (joined
+      (portRef Q (instanceRef BU74))
+      (portRef I0 (instanceRef BU104))
+      (portRef D (instanceRef BU195))
+    )
+   )
+   (net N930
+    (joined
+      (portRef Q (instanceRef BU67))
+      (portRef I0 (instanceRef BU100))
+      (portRef D (instanceRef BU193))
+    )
+   )
+   (net N931
+    (joined
+      (portRef Q (instanceRef BU60))
+      (portRef I0 (instanceRef BU96))
+      (portRef D (instanceRef BU191))
+    )
+   )
+   (net N936
+    (joined
+      (portRef Q (instanceRef BU197))
+      (portRef D (instanceRef BU214))
+      (portRef D (instanceRef BU221))
+    )
+   )
+   (net N937
+    (joined
+      (portRef Q (instanceRef BU195))
+      (portRef D (instanceRef BU210))
+      (portRef D (instanceRef BU217))
+    )
+   )
+   (net N938
+    (joined
+      (portRef Q (instanceRef BU193))
+      (portRef D (instanceRef BU207))
+      (portRef D (instanceRef BU209))
+    )
+   )
+   (net N939
+    (joined
+      (portRef Q (instanceRef BU191))
+      (portRef D (instanceRef BU202))
+      (portRef D (instanceRef BU204))
+    )
+   )
+   (net N940
+    (joined
+      (portRef Q (instanceRef BU221))
+      (portRef D (instanceRef BU222))
+    )
+   )
+   (net N941
+    (joined
+      (portRef Q (instanceRef BU217))
+      (portRef D (instanceRef BU218))
+    )
+   )
+   (net N942
+    (joined
+      (portRef Q (instanceRef BU207))
+      (portRef D (instanceRef BU208))
+    )
+   )
+   (net N943
+    (joined
+      (portRef Q (instanceRef BU202))
+      (portRef D (instanceRef BU203))
+    )
+   )
+   (net N960
+    (joined
+      (portRef D (instanceRef BU99))
+      (portRef D (instanceRef BU106))
+      (portRef Q (instanceRef BU186))
+      (portRef I0 (instanceRef BU223))
+    )
+   )
+   (net N961
+    (joined
+      (portRef D (instanceRef BU95))
+      (portRef D (instanceRef BU102))
+      (portRef Q (instanceRef BU179))
+      (portRef I0 (instanceRef BU219))
+    )
+   )
+   (net N962
+    (joined
+      (portRef D (instanceRef BU92))
+      (portRef D (instanceRef BU94))
+      (portRef Q (instanceRef BU172))
+      (portRef I0 (instanceRef BU215))
+    )
+   )
+   (net N963
+    (joined
+      (portRef D (instanceRef BU87))
+      (portRef D (instanceRef BU89))
+      (portRef Q (instanceRef BU165))
+      (portRef I0 (instanceRef BU211))
+    )
+   )
+   (net N968
+    (joined
+      (portRef Q (instanceRef BU106))
+      (portRef D (instanceRef BU107))
+    )
+   )
+   (net N969
+    (joined
+      (portRef Q (instanceRef BU102))
+      (portRef D (instanceRef BU103))
+    )
+   )
+   (net N970
+    (joined
+      (portRef Q (instanceRef BU92))
+      (portRef D (instanceRef BU93))
+    )
+   )
+   (net N971
+    (joined
+      (portRef Q (instanceRef BU87))
+      (portRef D (instanceRef BU88))
+    )
+   )
+   (net N1137
+    (joined
+      (portRef O (instanceRef BU32))
+      (portRef D (instanceRef BU34))
+    )
+   )
+   (net N1138
+    (joined
+      (portRef O (instanceRef BU38))
+      (portRef D (instanceRef BU40))
+    )
+   )
+   (net N1139
+    (joined
+      (portRef O (instanceRef BU44))
+      (portRef D (instanceRef BU46))
+    )
+   )
+   (net N1140
+    (joined
+      (portRef O (instanceRef BU49))
+      (portRef D (instanceRef BU51))
+    )
+   )
+   (net N1141
+    (joined
+      (portRef S (instanceRef BU31))
+      (portRef LI (instanceRef BU32))
+      (portRef O (instanceRef BU30))
+    )
+   )
+   (net N1143
+    (joined
+      (portRef O (instanceRef BU31))
+      (portRef CI (instanceRef BU37))
+      (portRef CI (instanceRef BU38))
+    )
+   )
+   (net N1146
+    (joined
+      (portRef S (instanceRef BU37))
+      (portRef LI (instanceRef BU38))
+      (portRef O (instanceRef BU36))
+    )
+   )
+   (net N1148
+    (joined
+      (portRef O (instanceRef BU37))
+      (portRef CI (instanceRef BU43))
+      (portRef CI (instanceRef BU44))
+    )
+   )
+   (net N1151
+    (joined
+      (portRef S (instanceRef BU43))
+      (portRef LI (instanceRef BU44))
+      (portRef O (instanceRef BU42))
+    )
+   )
+   (net N1153
+    (joined
+      (portRef O (instanceRef BU43))
+      (portRef CI (instanceRef BU49))
+    )
+   )
+   (net N1156
+    (joined
+      (portRef LI (instanceRef BU49))
+      (portRef O (instanceRef BU48))
+    )
+   )
+   (net N1332
+    (joined
+      (portRef D (instanceRef BU60))
+      (portRef O (instanceRef BU59))
+    )
+   )
+   (net N1372
+    (joined
+      (portRef D (instanceRef BU67))
+      (portRef O (instanceRef BU66))
+    )
+   )
+   (net N1412
+    (joined
+      (portRef D (instanceRef BU74))
+      (portRef O (instanceRef BU73))
+    )
+   )
+   (net N1452
+    (joined
+      (portRef D (instanceRef BU81))
+      (portRef O (instanceRef BU80))
+    )
+   )
+   (net N1471
+    (joined
+      (portRef Q (instanceRef BU99))
+      (portRef I1 (instanceRef BU108))
+    )
+   )
+   (net N1472
+    (joined
+      (portRef Q (instanceRef BU95))
+      (portRef I1 (instanceRef BU104))
+    )
+   )
+   (net N1473
+    (joined
+      (portRef Q (instanceRef BU94))
+      (portRef I1 (instanceRef BU100))
+    )
+   )
+   (net N1474
+    (joined
+      (portRef Q (instanceRef BU89))
+      (portRef I1 (instanceRef BU96))
+    )
+   )
+   (net N1475
+    (joined
+      (portRef Q (instanceRef BU107))
+      (portRef I2 (instanceRef BU108))
+    )
+   )
+   (net N1476
+    (joined
+      (portRef Q (instanceRef BU103))
+      (portRef I2 (instanceRef BU104))
+    )
+   )
+   (net N1477
+    (joined
+      (portRef Q (instanceRef BU93))
+      (portRef I2 (instanceRef BU100))
+    )
+   )
+   (net N1478
+    (joined
+      (portRef Q (instanceRef BU88))
+      (portRef I2 (instanceRef BU96))
+    )
+   )
+   (net N1479
+    (joined
+      (portRef O (instanceRef BU108))
+      (portRef S (instanceRef BU109))
+    )
+   )
+   (net N1480
+    (joined
+      (portRef O (instanceRef BU104))
+      (portRef S (instanceRef BU105))
+    )
+   )
+   (net N1481
+    (joined
+      (portRef O (instanceRef BU100))
+      (portRef S (instanceRef BU101))
+    )
+   )
+   (net N1482
+    (joined
+      (portRef O (instanceRef BU96))
+      (portRef S (instanceRef BU97))
+    )
+   )
+   (net N1483
+    (joined
+      (portRef LO (instanceRef BU109))
+      (portRef CI (instanceRef BU112))
+    )
+   )
+   (net N1484
+    (joined
+      (portRef O (instanceRef BU105))
+      (portRef CI (instanceRef BU109))
+    )
+   )
+   (net N1485
+    (joined
+      (portRef O (instanceRef BU101))
+      (portRef CI (instanceRef BU105))
+    )
+   )
+   (net N1486
+    (joined
+      (portRef O (instanceRef BU97))
+      (portRef CI (instanceRef BU101))
+    )
+   )
+   (net N1488
+    (joined
+      (portRef O (instanceRef BU85))
+      (portRef CE (instanceRef BU113))
+    )
+   )
+   (net N1489
+    (joined
+      (portRef O (instanceRef BU112))
+      (portRef D (instanceRef BU113))
+    )
+   )
+   (net N1490
+    (joined
+      (portRef O (instanceRef BU90))
+      (portRef S (instanceRef BU91))
+    )
+   )
+   (net N1685
+    (joined
+      (portRef O (instanceRef BU137))
+      (portRef D (instanceRef BU139))
+    )
+   )
+   (net N1686
+    (joined
+      (portRef O (instanceRef BU143))
+      (portRef D (instanceRef BU145))
+    )
+   )
+   (net N1687
+    (joined
+      (portRef O (instanceRef BU149))
+      (portRef D (instanceRef BU151))
+    )
+   )
+   (net N1688
+    (joined
+      (portRef O (instanceRef BU154))
+      (portRef D (instanceRef BU156))
+    )
+   )
+   (net N1689
+    (joined
+      (portRef S (instanceRef BU136))
+      (portRef LI (instanceRef BU137))
+      (portRef O (instanceRef BU135))
+    )
+   )
+   (net N1691
+    (joined
+      (portRef O (instanceRef BU136))
+      (portRef CI (instanceRef BU142))
+      (portRef CI (instanceRef BU143))
+    )
+   )
+   (net N1694
+    (joined
+      (portRef S (instanceRef BU142))
+      (portRef LI (instanceRef BU143))
+      (portRef O (instanceRef BU141))
+    )
+   )
+   (net N1696
+    (joined
+      (portRef O (instanceRef BU142))
+      (portRef CI (instanceRef BU148))
+      (portRef CI (instanceRef BU149))
+    )
+   )
+   (net N1699
+    (joined
+      (portRef S (instanceRef BU148))
+      (portRef LI (instanceRef BU149))
+      (portRef O (instanceRef BU147))
+    )
+   )
+   (net N1701
+    (joined
+      (portRef O (instanceRef BU148))
+      (portRef CI (instanceRef BU154))
+    )
+   )
+   (net N1704
+    (joined
+      (portRef LI (instanceRef BU154))
+      (portRef O (instanceRef BU153))
+    )
+   )
+   (net N1880
+    (joined
+      (portRef D (instanceRef BU165))
+      (portRef O (instanceRef BU164))
+    )
+   )
+   (net N1920
+    (joined
+      (portRef D (instanceRef BU172))
+      (portRef O (instanceRef BU171))
+    )
+   )
+   (net N1960
+    (joined
+      (portRef D (instanceRef BU179))
+      (portRef O (instanceRef BU178))
+    )
+   )
+   (net N2000
+    (joined
+      (portRef D (instanceRef BU186))
+      (portRef O (instanceRef BU185))
+    )
+   )
+   (net N2077
+    (joined
+      (portRef Q (instanceRef BU214))
+      (portRef I1 (instanceRef BU223))
+    )
+   )
+   (net N2078
+    (joined
+      (portRef Q (instanceRef BU210))
+      (portRef I1 (instanceRef BU219))
+    )
+   )
+   (net N2079
+    (joined
+      (portRef Q (instanceRef BU209))
+      (portRef I1 (instanceRef BU215))
+    )
+   )
+   (net N2080
+    (joined
+      (portRef Q (instanceRef BU204))
+      (portRef I1 (instanceRef BU211))
+    )
+   )
+   (net N2081
+    (joined
+      (portRef Q (instanceRef BU222))
+      (portRef I2 (instanceRef BU223))
+    )
+   )
+   (net N2082
+    (joined
+      (portRef Q (instanceRef BU218))
+      (portRef I2 (instanceRef BU219))
+    )
+   )
+   (net N2083
+    (joined
+      (portRef Q (instanceRef BU208))
+      (portRef I2 (instanceRef BU215))
+    )
+   )
+   (net N2084
+    (joined
+      (portRef Q (instanceRef BU203))
+      (portRef I2 (instanceRef BU211))
+    )
+   )
+   (net N2085
+    (joined
+      (portRef O (instanceRef BU223))
+      (portRef S (instanceRef BU224))
+    )
+   )
+   (net N2086
+    (joined
+      (portRef O (instanceRef BU219))
+      (portRef S (instanceRef BU220))
+    )
+   )
+   (net N2087
+    (joined
+      (portRef O (instanceRef BU215))
+      (portRef S (instanceRef BU216))
+    )
+   )
+   (net N2088
+    (joined
+      (portRef O (instanceRef BU211))
+      (portRef S (instanceRef BU212))
+    )
+   )
+   (net N2089
+    (joined
+      (portRef LO (instanceRef BU224))
+      (portRef CI (instanceRef BU227))
+    )
+   )
+   (net N2090
+    (joined
+      (portRef O (instanceRef BU220))
+      (portRef CI (instanceRef BU224))
+    )
+   )
+   (net N2091
+    (joined
+      (portRef O (instanceRef BU216))
+      (portRef CI (instanceRef BU220))
+    )
+   )
+   (net N2092
+    (joined
+      (portRef O (instanceRef BU212))
+      (portRef CI (instanceRef BU216))
+    )
+   )
+   (net N2094
+    (joined
+      (portRef O (instanceRef BU200))
+      (portRef CE (instanceRef BU228))
+    )
+   )
+   (net N2095
+    (joined
+      (portRef O (instanceRef BU227))
+      (portRef D (instanceRef BU228))
+    )
+   )
+   (net N2096
+    (joined
+      (portRef O (instanceRef BU205))
+      (portRef S (instanceRef BU206))
+    )
+   )
+))))
+(design fifo (cellRef fifo (libraryRef test_lib))
+  (property X_CORE_INFO (string "async_fifo_v6_1, Coregen 8.1.02i_ip1"))
+  (property PART (string "xc3s400-pq208-5") (owner "Xilinx")))
+)
diff -r 7390b436dd20 -r f88da01700da fifo.sym
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.sym	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,57 @@
+VERSION 5
+BEGIN SYMBOL fifo
+SYMBOLTYPE BLOCK
+TIMESTAMP 2006 2 21 5 25 26
+SYMPIN 192 480 Input ainit
+SYMPIN 0 48 Input din[3:0]
+SYMPIN 0 144 Input wr_en
+SYMPIN 0 176 Input wr_clk
+SYMPIN 0 368 Input rd_en
+SYMPIN 0 400 Input rd_clk
+SYMPIN 384 48 Output full
+SYMPIN 384 240 Output dout[3:0]
+SYMPIN 384 272 Output empty
+RECTANGLE N 32 0 352 448 
+BEGIN DISPLAY 192 444 PIN ainit ATTR PinName
+    ALIGNMENT BCENTER
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 192 448 192 480 
+BEGIN DISPLAY 36 48 PIN din[3:0] ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 0 48 32 48 
+END LINE
+BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 144 32 144 
+BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 176 32 176 
+BEGIN DISPLAY 36 368 PIN rd_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 368 32 368 
+BEGIN DISPLAY 36 400 PIN rd_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 400 32 400 
+BEGIN DISPLAY 348 48 PIN full ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 352 48 384 48 
+BEGIN DISPLAY 348 240 PIN dout[3:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 352 240 384 240 
+END LINE
+BEGIN DISPLAY 348 272 PIN empty ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 352 272 384 272 
+END SYMBOL
diff -r 7390b436dd20 -r f88da01700da fifo.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.v	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,114 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2006 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synopsys directives "translate_off/translate_on" specified below are
+// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo.v when simulating
+// the core, fifo. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo(
+	din,
+	wr_en,
+	wr_clk,
+	rd_en,
+	rd_clk,
+	ainit,
+	dout,
+	full,
+	empty);
+
+
+input [3 : 0] din;
+input wr_en;
+input wr_clk;
+input rd_en;
+input rd_clk;
+input ainit;
+output [3 : 0] dout;
+output full;
+output empty;
+
+// synopsys translate_off
+
+      ASYNC_FIFO_V6_1 #(
+		4,	// c_data_width
+		0,	// c_enable_rlocs
+		15,	// c_fifo_depth
+		0,	// c_has_almost_empty
+		0,	// c_has_almost_full
+		0,	// c_has_rd_ack
+		0,	// c_has_rd_count
+		0,	// c_has_rd_err
+		0,	// c_has_wr_ack
+		0,	// c_has_wr_count
+		0,	// c_has_wr_err
+		0,	// c_rd_ack_low
+		2,	// c_rd_count_width
+		0,	// c_rd_err_low
+		1,	// c_use_blockmem
+		0,	// c_wr_ack_low
+		2,	// c_wr_count_width
+		0)	// c_wr_err_low
+	inst (
+		.DIN(din),
+		.WR_EN(wr_en),
+		.WR_CLK(wr_clk),
+		.RD_EN(rd_en),
+		.RD_CLK(rd_clk),
+		.AINIT(ainit),
+		.DOUT(dout),
+		.FULL(full),
+		.EMPTY(empty),
+		.ALMOST_FULL(),
+		.ALMOST_EMPTY(),
+		.WR_COUNT(),
+		.RD_COUNT(),
+		.RD_ACK(),
+		.RD_ERR(),
+		.WR_ACK(),
+		.WR_ERR());
+
+
+// synopsys translate_on
+
+// FPGA Express black box declaration
+// synopsys attribute fpga_dont_touch "true"
+// synthesis attribute fpga_dont_touch of fifo is "true"
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of fifo is "black_box"
+
+endmodule
+
diff -r 7390b436dd20 -r f88da01700da fifo.veo
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.veo	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,51 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2006 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo YourInstanceName (
+	.din(din),
+	.wr_en(wr_en),
+	.wr_clk(wr_clk),
+	.rd_en(rd_en),
+	.rd_clk(rd_clk),
+	.ainit(ainit),
+	.dout(dout),
+	.full(full),
+	.empty(empty));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo.v when simulating
+// the core, fifo. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff -r 7390b436dd20 -r f88da01700da fifo.vhd
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.vhd	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,109 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2006 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo.vhd when simulating
+-- the core, fifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synopsys directives "translate_off/translate_on" specified
+-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synopsys translate_off
+Library XilinxCoreLib;
+-- synopsys translate_on
+ENTITY fifo IS
+	port (
+	din: IN std_logic_VECTOR(3 downto 0);
+	wr_en: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rd_clk: IN std_logic;
+	ainit: IN std_logic;
+	dout: OUT std_logic_VECTOR(3 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic);
+END fifo;
+
+ARCHITECTURE fifo_a OF fifo IS
+-- synopsys translate_off
+component wrapped_fifo
+	port (
+	din: IN std_logic_VECTOR(3 downto 0);
+	wr_en: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rd_clk: IN std_logic;
+	ainit: IN std_logic;
+	dout: OUT std_logic_VECTOR(3 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic);
+end component;
+
+-- Configuration specification 
+	for all : wrapped_fifo use entity XilinxCoreLib.async_fifo_v6_1(behavioral)
+		generic map(
+			c_use_blockmem => 1,
+			c_rd_count_width => 2,
+			c_has_wr_ack => 0,
+			c_has_almost_full => 0,
+			c_has_wr_err => 0,
+			c_wr_err_low => 0,
+			c_wr_ack_low => 0,
+			c_data_width => 4,
+			c_enable_rlocs => 0,
+			c_rd_err_low => 0,
+			c_rd_ack_low => 0,
+			c_wr_count_width => 2,
+			c_has_rd_count => 0,
+			c_has_almost_empty => 0,
+			c_has_rd_ack => 0,
+			c_has_wr_count => 0,
+			c_fifo_depth => 15,
+			c_has_rd_err => 0);
+-- synopsys translate_on
+BEGIN
+-- synopsys translate_off
+U0 : wrapped_fifo
+		port map (
+			din => din,
+			wr_en => wr_en,
+			wr_clk => wr_clk,
+			rd_en => rd_en,
+			rd_clk => rd_clk,
+			ainit => ainit,
+			dout => dout,
+			full => full,
+			empty => empty);
+-- synopsys translate_on
+
+END fifo_a;
+
diff -r 7390b436dd20 -r f88da01700da fifo.vho
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.vho	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,76 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2006 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component fifo
+	port (
+	din: IN std_logic_VECTOR(3 downto 0);
+	wr_en: IN std_logic;
+	wr_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rd_clk: IN std_logic;
+	ainit: IN std_logic;
+	dout: OUT std_logic_VECTOR(3 downto 0);
+	full: OUT std_logic;
+	empty: OUT std_logic);
+end component;
+
+-- FPGA Express Black Box declaration
+attribute fpga_dont_touch: string;
+attribute fpga_dont_touch of fifo: component is "true";
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of fifo: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo
+		port map (
+			din => din,
+			wr_en => wr_en,
+			wr_clk => wr_clk,
+			rd_en => rd_en,
+			rd_clk => rd_clk,
+			ainit => ainit,
+			dout => dout,
+			full => full,
+			empty => empty);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file fifo.vhd when simulating
+-- the core, fifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
diff -r 7390b436dd20 -r f88da01700da fifo.xco
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.xco	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,46 @@
+# BEGIN Project Options
+SET flowvendor = Foundation_iSE
+SET vhdlsim = True
+SET verilogsim = True
+SET workingdirectory = C:\Temp\Memec-test
+SET speedgrade = -5
+SET simulationfiles = Behavioral
+SET asysymbol = True
+SET addpads = False
+SET device = xc3s400
+SET implementationfiletype = Edif
+SET busformat = BusFormatAngleBracketNotRipped
+SET foundationsym = False
+SET package = pq208
+SET createndf = False
+SET designentry = VHDL
+SET devicefamily = spartan3
+SET formalverification = False
+SET removerpms = False
+# END Project Options
+# BEGIN Select
+SELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET create_rpm=false
+CSET read_acknowledge=false
+CSET almost_empty_flag=false
+CSET write_acknowledge=false
+CSET memory_type=block
+CSET read_acknowledge_sense=active_high
+CSET read_count_width=2
+CSET fifo_depth=15
+CSET component_name=fifo
+CSET write_count_width=2
+CSET write_count=false
+CSET read_count=false
+CSET write_error=false
+CSET read_error=false
+CSET read_error_sense=active_high
+CSET almost_full_flag=false
+CSET write_acknowledge_sense=active_high
+CSET write_error_sense=active_high
+CSET input_data_width=4
+# END Parameters
+GENERATE
+
diff -r 7390b436dd20 -r f88da01700da fifo_top.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo_top.v	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    18:33:04 02/21/2006 
+// Design Name: 
+// Module Name:    fifo_top 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module fifo_top(din, wr_en, wr_clk, rd_en, rd_clk, ainit, dout, full, empty);
+   input [3:0] din;
+   input       wr_en;
+   input       wr_clk;
+   input       rd_en;
+   input       rd_clk;
+   input       ainit;
+
+   output [3:0] dout;
+   output 	full;
+   output 	empty;
+   
+   fifo FIFO (
+	      .din(din),
+	      .wr_en(wr_en),
+	      .wr_clk(wr_clk),
+	      .rd_en(rd_en),
+	      .rd_clk(rd_clk),
+	      .ainit(ainit),
+	      .dout(dout),
+	      .full(full),
+	      .empty(empty)
+	      );
+
+endmodule
diff -r 7390b436dd20 -r f88da01700da filter.filter
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/filter.filter	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,7 @@
+<!--                                                                                                 -->
+<!--This is an internal file that has been generated by the Xilinx ISE software.  Any direct         -->
+<!--editing of this file may result in data corruption or in unpredictable behavior.  It is strongly -->
+<!--advised that users do not directly edit the contents of this file.                               -->
+<!--                                                                                                 -->
+<filters xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation='filter.xsd'>
+</filters>
diff -r 7390b436dd20 -r f88da01700da memec-test.ipf
Binary file memec-test.ipf has changed
diff -r 7390b436dd20 -r f88da01700da test.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test.v	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,208 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:00:14 02/18/2006 
+// Design Name: 
+// Module Name:    test 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module test(CLK, PUSH, DIP, DISPLAY, LED, FIFO_DIN, FIFO_DOUT, FIFO_RDCLK, FIFO_RDEN, FIFO_WRCLK, FIFO_WREN, FIFO_RESET, FIFO_FULL, FIFO_EMPTY);
+
+   // Input Declarations
+   input           CLK;          //surface-mount 50MHz oscillator
+   input [2:1] 	   PUSH;         //push-button switches
+   input [3:0] 	   DIP;          //DIP[3] is SW3[1] on the board
+   input [3:0]     FIFO_DOUT;
+   input           FIFO_FULL;
+   input           FIFO_EMPTY;
+  
+   // Output Declarations
+   output [6:0]    DISPLAY;      //7-segment display DD1
+   output [3:0]    LED;          //user LEDs
+   output [3:0]    FIFO_DIN;
+   output          FIFO_RDCLK;
+   output          FIFO_RDEN;
+   output          FIFO_WRCLK;
+   output          FIFO_WREN;
+   output          FIFO_RESET;
+   
+   // Input Registers
+   reg [3:0] 	   DIP_r [3:0]; // 4x4 array to hold registered versions of DIP
+   reg [3:0] 	   DIP_d;       // debounced DIP
+   reg [3:0] 	   PUSH1_r;     // registered version of PUSH1
+   reg [3:0] 	   PUSH2_r;     // registered version of PUSH2
+   reg             PUSH1_d;     // debounced PUSH1
+   reg             PUSH2_d;     // debounced PUSH2
+
+   // Output Registers
+   reg [3:0] 	   LED;
+   reg [6:0] 	   DISPLAY;
+   reg 		   FIFO_WREN;
+   reg 		   FIFO_WRCLK;
+   reg 		   FIFO_RDEN;
+   reg 		   FIFO_RDCLK;
+   reg [3:0] 	   FIFO_DIN;
+   reg 		   FIFO_RESET;
+   
+   // Other Registers
+   reg [22:0] 	   sec_cnt; // Count clocks for sec_en
+   reg             reset;   // high-asserted reset
+   reg 		   ledtog;
+   reg 		   direction;
+ 		   
+   // Internal signals
+   wire            sec_en; // Asserted on the second
+   integer         i;
+   
+   // Register and debounce push buttons and switches
+   // If the bouncy signal is high, 4 consecutive lows required to pull it low
+   // If the bouncy signal is low, 4 consecutive highs required to pull it high
+   always @(posedge CLK) begin
+      PUSH1_r[0] <= PUSH[1];
+      PUSH1_r[1] <= PUSH1_r[0];
+      PUSH1_r[2] <= PUSH1_r[1];
+      PUSH1_r[3] <= PUSH1_r[2];
+      if(PUSH1_d)
+        PUSH1_d <= |PUSH1_r;  
+      else
+        PUSH1_d <= &PUSH1_r;
+
+      reset      <= ~PUSH1_d;
+
+      PUSH2_r[0] <= PUSH[2];
+      PUSH2_r[1] <= PUSH2_r[0];
+      PUSH2_r[2] <= PUSH2_r[1];
+      PUSH2_r[3] <= PUSH2_r[2];
+      if(PUSH2_d)
+        PUSH2_d <= |PUSH2_r;  
+      else
+        PUSH2_d <= &PUSH2_r;
+
+      // Register the 4-bit DIP switch 4 times
+      DIP_r[0]      <= DIP;
+      DIP_r[1]      <= DIP_r[0];
+      DIP_r[2]      <= DIP_r[1];
+      DIP_r[3]      <= DIP_r[2];
+
+      // Debounce the DIPs based on the register contents
+      // For each bit, 0 through 3, switch polarity only when 4 opposite
+      //     polarity is seen for four consecutive clocks.
+      for (i = 0; i < 4; i = i+1)
+	begin
+           if(DIP_d[i])
+             DIP_d[i] <= DIP_r[0][i] | DIP_r[1][i] | DIP_r[2][i] | DIP_r[3][i];
+           else 
+             DIP_d[i] <= DIP_r[0][i] & DIP_r[1][i] & DIP_r[2][i] & DIP_r[3][i];
+	end
+
+   end
+
+   
+   // Show FIFO status on LEDs
+   always @(posedge CLK) begin
+      if (reset) begin
+	 LED <= 4'b0111;
+	 DISPLAY <= 7'b1111111;
+      end else begin
+//	 LED <= (ledtog | (FIFO_EMPTY << 1) | (FIFO_FULL << 2) | (PUSH2_d << 3));
+	 LED <= {PUSH2_d, ~FIFO_FULL, ~FIFO_EMPTY, ledtog};
+	
+	 if (PUSH2_d)
+	    DISPLAY <= NUM2SEG(~DIP_d);
+	 else
+	    DISPLAY <= NUM2SEG(FIFO_DOUT);
+      end // else: !if(reset)
+   end // always @ (posedge CLK)
+   
+   always @(posedge CLK or negedge CLK) begin
+      if (CLK) begin
+	 FIFO_WRCLK <= 1;
+	 FIFO_RDCLK <= 1;
+      end else begin
+	 FIFO_WRCLK <= 0;
+	 FIFO_RDCLK <= 0;
+      end
+   end
+   
+   // Count 3.125Mhz clocks to drive the second tick
+   always @(posedge CLK) begin
+      if (reset) begin
+	 ledtog <= 0;
+         sec_cnt <= 0;
+	 FIFO_DIN <= 0;
+	 FIFO_WREN <= 0;
+	 FIFO_RDEN <= 0;
+	 FIFO_RESET <= 1;
+	 direction <= 0; // Write
+      end else begin
+	 FIFO_RESET <= 0;
+	 // Drive FIFO input from debounced DIP switches
+	 FIFO_DIN <= ~(DIP_d);
+	 
+	 // Hit the second mark?
+         if (sec_en) begin
+            sec_cnt <= 0;
+	    
+	    // FIFO
+	    if (FIFO_FULL)
+	      direction <= 0;
+
+	    if (FIFO_EMPTY)
+	      direction <= 1;
+	    
+	    if (direction)
+	      FIFO_WREN <= 1;
+	    else
+	      FIFO_RDEN <= 1;
+	    
+	    ledtog <= ~ledtog;
+         end else begin // sec_en
+            sec_cnt <= sec_cnt + 1;
+	    FIFO_WREN <= 0;
+	    FIFO_RDEN <= 0;
+	 end
+      end
+   end // always @ (posedge CLK)
+   
+   // Create 1-second count
+   assign   sec_en  = (sec_cnt == 22'd3_125_000);
+
+   // Convert a number into hex for the 7 segment display
+   function [6:0] NUM2SEG;
+      input [3:0] num;
+      begin
+	 case (num)
+	   0:    NUM2SEG   = ~(7'b0111111); 
+	   1:    NUM2SEG   = ~(7'b0000110); 
+	   2:    NUM2SEG   = ~(7'b1011011); 
+	   3:    NUM2SEG   = ~(7'b1001111); 
+	   4:    NUM2SEG   = ~(7'b1100110); 
+	   5:    NUM2SEG   = ~(7'b1101101); 
+	   6:    NUM2SEG   = ~(7'b1111101); 
+	   7:    NUM2SEG   = ~(7'b0000111); 
+	   8:    NUM2SEG   = ~(7'b1111111); 
+	   9:    NUM2SEG   = ~(7'b1101111);
+	   4'hA: NUM2SEG   = ~(7'b1110111); 
+	   4'hb: NUM2SEG   = ~(7'b1111100); 
+	   4'hC: NUM2SEG   = ~(7'b0111001); 
+	   4'hd: NUM2SEG   = ~(7'b1011110); 
+	   4'hE: NUM2SEG   = ~(7'b1111001); 
+	   4'hF: NUM2SEG   = ~(7'b1110001); 
+	   default:   NUM2SEG   = 7'b1111111;
+	 endcase // case(~num)
+      end
+   endfunction
+      
+endmodule
diff -r 7390b436dd20 -r f88da01700da test_test.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_test.v	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,81 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   16:48:57 02/22/2006
+// Design Name:   test
+// Module Name:   test_test.v
+// Project Name:  Memec-test
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: test
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module test_test_v;
+
+   // Inputs
+   reg CLK;
+   reg [2:1] PUSH;
+   reg [3:0] DIP;
+   reg [3:0] FIFO_DOUT;
+   reg 	     FIFO_FULL;
+   reg 	     FIFO_EMPTY;
+
+   // Outputs
+   wire [6:0] DISPLAY;
+   wire [3:0] LED;
+   wire [3:0] FIFO_DIN;
+   wire       FIFO_RDCLK;
+   wire       FIFO_RDEN;
+   wire       FIFO_WRCLK;
+   wire       FIFO_WREN;
+   wire       FIFO_RESET;
+
+   // Instantiate the Unit Under Test (UUT)
+   test uut (
+	     .CLK(CLK), 
+	     .PUSH(PUSH), 
+	     .DIP(DIP), 
+	     .DISPLAY(DISPLAY), 
+	     .LED(LED), 
+	     .FIFO_DIN(FIFO_DIN), 
+	     .FIFO_DOUT(FIFO_DOUT), 
+	     .FIFO_RDCLK(FIFO_RDCLK), 
+	     .FIFO_RDEN(FIFO_RDEN), 
+	     .FIFO_WRCLK(FIFO_WRCLK), 
+	     .FIFO_WREN(FIFO_WREN), 
+	     .FIFO_RESET(FIFO_RESET), 
+	     .FIFO_FULL(FIFO_FULL), 
+	     .FIFO_EMPTY(FIFO_EMPTY)
+	     );
+
+   initial begin
+      // Initialize Inputs
+      CLK = 0;
+      PUSH = 0;
+      DIP = 0;
+      FIFO_DOUT = 0;
+      FIFO_FULL = 0;
+      FIFO_EMPTY = 0;
+
+      // Wait 100 ns for global reset to finish
+      #100;
+   end
+
+   always begin
+      #5 CLK = ~CLK; // Toggle clock every 5 ticks
+   end
+   
+endmodule
+
diff -r 7390b436dd20 -r f88da01700da toplevel.ucf
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/toplevel.ucf	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,46 @@
+# Specify a 50 MHz constraint with a Divide-by-16 in the DLL
+NET      "CLK" TNM_NET = "CLK";
+TIMESPEC "TS_CLK" = PERIOD "CLK" 50 MHz HIGH 50 %;
+
+# I/O Placement and timing constraints
+
+# Specify set-up and clk-out times
+OFFSET = IN  5.0 ns BEFORE "CLK";
+OFFSET = OUT 5.0 ns AFTER  "CLK";
+
+# Locate DCM & BUFG to ensure they are on the same side as the clk pin
+INST "dcm_div16" LOC = "DCM_X0Y1"  ;
+INST "U3"            LOC = "BUFGMUX7"  ;
+INST "U4"            LOC = "BUFGMUX6"  ;
+
+# I/O input constraints
+NET "CLK"   LOC = "P184" | IOSTANDARD = LVCMOS33; # SMT clock, JP30 must have jumper at 1-2
+# NET "CLK"   LOC = "P183"; # clock socket
+
+NET "PUSH<1>"      LOC = "P22";
+NET "PUSH<2>"      LOC = "P24";
+NET "PUSH<*>"      PULLUP | IOSTANDARD = LVCMOS33;
+
+NET "DIP<3>"       LOC = "P26";
+NET "DIP<2>"       LOC = "P27";
+NET "DIP<1>"       LOC = "P28";
+NET "DIP<0>"       LOC = "P29";
+NET "DIP<*>"       PULLUP | IOSTANDARD = LVCMOS33;
+
+# I/O Output Constraints
+NET "DISPLAY<0>"   LOC = "P36"; # DISPLAY.1A
+NET "DISPLAY<1>"   LOC = "P37"; # DISPLAY.1B
+NET "DISPLAY<2>"   LOC = "P39"; # DISPLAY.1C
+NET "DISPLAY<3>"   LOC = "P33"; # DISPLAY.1D
+NET "DISPLAY<4>"   LOC = "P31"; # DISPLAY.1E
+NET "DISPLAY<5>"   LOC = "P34"; # DISPLAY.1F
+NET "DISPLAY<6>"   LOC = "P35"; # DISPLAY.1G
+NET "DISPLAY<*>"   FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;
+
+NET "LED<0>"       LOC = "P19";
+NET "LED<1>"       LOC = "P18";
+NET "LED<2>"       LOC = "P21";
+NET "LED<3>"       LOC = "P20";
+NET "LED<*>"       FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;
+
+NET "RIO_A03"	   LOC = "P128" | IOSTANDARD = LVCMOS33 | FAST | DRIVE = 24;
\ No newline at end of file