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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
parents f88da01700da
children
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 # Specify a 50 MHz constraint with a Divide-by-16 in the DLL
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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2 NET "CLK" TNM_NET = "CLK";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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3 TIMESPEC "TS_CLK" = PERIOD "CLK" 50 MHz HIGH 50 %;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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5 # I/O Placement and timing constraints
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
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7 # Specify set-up and clk-out times
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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8 OFFSET = IN 5.0 ns BEFORE "CLK";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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9 OFFSET = OUT 5.0 ns AFTER "CLK";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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11 # Locate DCM & BUFG to ensure they are on the same side as the clk pin
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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12 INST "dcm_div16" LOC = "DCM_X0Y1" ;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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13 INST "U3" LOC = "BUFGMUX7" ;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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14 INST "U4" LOC = "BUFGMUX6" ;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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16 # I/O input constraints
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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17 NET "CLK" LOC = "P184" | IOSTANDARD = LVCMOS33; # SMT clock, JP30 must have jumper at 1-2
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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18 # NET "CLK" LOC = "P183"; # clock socket
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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19
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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20 NET "PUSH<1>" LOC = "P22";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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21 NET "PUSH<2>" LOC = "P24";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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22 NET "PUSH<*>" PULLUP | IOSTANDARD = LVCMOS33;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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24 NET "DIP<3>" LOC = "P26";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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25 NET "DIP<2>" LOC = "P27";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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26 NET "DIP<1>" LOC = "P28";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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27 NET "DIP<0>" LOC = "P29";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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28 NET "DIP<*>" PULLUP | IOSTANDARD = LVCMOS33;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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30 # I/O Output Constraints
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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31 NET "DISPLAY<0>" LOC = "P36"; # DISPLAY.1A
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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32 NET "DISPLAY<1>" LOC = "P37"; # DISPLAY.1B
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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33 NET "DISPLAY<2>" LOC = "P39"; # DISPLAY.1C
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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34 NET "DISPLAY<3>" LOC = "P33"; # DISPLAY.1D
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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35 NET "DISPLAY<4>" LOC = "P31"; # DISPLAY.1E
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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36 NET "DISPLAY<5>" LOC = "P34"; # DISPLAY.1F
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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37 NET "DISPLAY<6>" LOC = "P35"; # DISPLAY.1G
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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38 NET "DISPLAY<*>" FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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39
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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40 NET "LED<0>" LOC = "P19";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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41 NET "LED<1>" LOC = "P18";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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42 NET "LED<2>" LOC = "P21";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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43 NET "LED<3>" LOC = "P20";
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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44 NET "LED<*>" FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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46 NET "RIO_A03" LOC = "P128" | IOSTANDARD = LVCMOS33 | FAST | DRIVE = 24;